本书系统介绍用于电子、光电子和MEMS器件的2.5D、3D以及3D IC集成和封装技术的前沿进展和演变趋势，讨论SD Ic集成和封装关键技术的主要工艺问题和解诀方案。主要内容包括半导体工业中的集成电路发展，摩尔定律的起源和演变历史，三维集成和封装的优势和挑战，TSV制程与模型、晶圆减薄与薄晶圆在封装组装过程中的拿持晶圆键合技术、三维堆叠的微凸点制作与组装技术、3D硅集成、2.5D/3D IC和无源转接板的3D IC集成、三维器件集成的热管理技术、封装基板技术，以及存储器、LED、MEMS、CIS 3D IC集成等关键技术问题，最后讨论PoP、Fanin WLP、eVLP、ePLP等技术。
Preface
1 3D Integration for Semiconductor IC Packaging
1.1 Introduction
1.2 3D Integration
1.3 3D IC Packaging
1.4 3D Si Integration
1.5 3D IC Integration
1.5.1 Hybrid Memory Cube
1.5.2 Wide I/O DRAM and Wide I/O 2
1.5.3 High Bandwidth Memory
1.5.4 Wide I/O Memory (or Logic-on-Logic)
1.5.5 Passive Interposer (2.5D IC Integration)
1.6 Supply Chains before the TSV Era
1.6.1 FEOL (Front-End-of-Line)
1.6.2 BEOL (Back-End-of-Line)
1.6.3 OSAT (Outsourced Semiconductor Assembly and Test)
1.7 Supply Chains for the TSV Era-Who Makes the TSV
1.7.1 TSVs Fabricated by the Via-First Process
1.7.2 TSVs Fabricated by the Via-Middle Process
1.7.3 TSVs Fabricated by the Via-Last (from the Front Side) Process
1.7.4 TSVs Fabricated by the Via-Last (from the Back Side) Process
1.7.5 How About the Passive TSV Interposers
1.7.6 Who Wants to Fabricate the TSV for Passive Interposers
1.7.7 Summary and Recommendations
1.8 Supply Chains for the TSV Era-Who Does the MEOL, Assembly, and Test
1.8.1 Wide I/O Memory (Face-to-Back) by TSV Via-Middle Fabrication Process
1.8.2 Wide I/O Memory (Face-to-Face) by TSV Via-Middle Fabrication Process
1.8.3 Wide I/O DRAM by TSV Via-Middle Fabrication Process
1.8.4 2.5D IC Integration with TSV/RDL Passive Interposers
1.8.5 Summary and Recommendations
1.9 CMOS Images Sensors with TSVs
1.9.1 Toshiba's DynastronTM
1.9.2 STMicroelectronics' VGA CIS Camera Module
1.9.3 Samsung's S5K4E5YX BSI CIS
1.9.4 Toshiba's HEW4 BSI TCM5103PL
1.9.5 Nemotek's CIS
1.9.6 SONY's ISX014 Stacked Camera Sensor
1.10 MEMS with TSVs
1.10.1 STMicroelectronics’ MEMS Inertial Sensors
1.10.2 Discera's MEME Resonator
1.10.3 Avago's FBAR MEMS Filter
1.11 References
2 Through-Silicon Vias Modeling and Testing
2.1 Introduction
2.2 Electrical Modeling of TSVs
2.2.1 Analytic Model and Equations for a Generic TSV Structure
2.2.2 Verification of the Proposed TSV Model in Frequency Domain
2.2.3 Verification of the Proposed TSV Model in Time Domain
2.2.4 TSV Electrical Design Guideline
2.2.5 Summary and Recommendations
2.3 Thermal Modeling of TSVs
2.3.1 Cu-Filled TSV Equivalent Thermal Conductivity Extraction
2.3.2 Thermal Behavior of a TSV Cell
2.3.3 Cu-Filled TSV Equivalent Thermal Conductivity Equations
2.3.4 Verification of the TSV Equivalent Thermal Conductivity Equations
2.3.5 Summary and Recommendations
2.4 Mechanical Modeling and Testing of TSVs
2.4.1 TEM between the Cu-Filled TSV and Its Surrounding Si
2.4.2 Experimental Results on Cu Pumping during Manufacturing
2.4.3 Cu Pumping under Thermal Shock Cycling
2.4.4 Keep-Out-Zone of Cu-Filled TSVs
2.4.5 Summary and Recommendations
2.5 References
3 Stress Sensors for Thin-Wafer Handling and Strength Measurement
4 Package Substrate Technologies
5 Microbumps: Fabrication, Assembly, and Reliability
6 3D Si Integration
7 2.5D/3D IC Integration
8 3D IC Integration with Passive Interposer
9 Thermal Management of 2.5D/3D IC Integration
10 Embedded 3D Hybrid Integration
11 3D LED and IC Integration
12 3D MEMS and IC Integration
13 3D CMOS Image Sensor and IC Integration
14 3D IC Packaging
Index
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